An image sensor is used to transform an optical image focused on the sensor into an electrical signal. The image sensor typically contains an array of light detecting elements, wherein each element produces an analog signal in response to the light intensity of an image impinging on the element when the image is focused on the array. These signals from the sensor array may then be used to display a corresponding image on a display.
One very well known type of the image sensor is the charge-coupled device (CCD). An integrated circuit chip containing CCD image sensors is expensive due to the specific process required. The CCD also requires relatively large power dissipation, because of the required clock signals and the high voltage that is usually needed. Compared with the CCD image sensor, a CMOS active pixel sensors (APS) has attracted much attention recently because of its capability of monolithic integration of the circuits of control, drive and signal processing into a single sensor chip. The advantages of the CMOS APS imager are: low voltage operation and low power consumption, process compatibility with on-chip electronics, and potentially lower cost, as compared with the conventional CCD. This is derived from the wide availability of a standard CMOS manufacturing process.
However, it has been well known that the CMOS image sensor suffers from noise issues which can adversely degrade the performance. These noises include kTC noise associated with the sampling of the image data; 1/f noise associated with the circuits used to amplify the image signal; and fixed pattern noise associated with non-uniformity, primarily between columns within the array. These noise issues significantly become major factors causing the CMOS active pixel sensor to have lower sensitivity or lower dynamic range compared to the CCD.
FIG. 1A illustrates the architecture of a conventional CMOS image sensor of 512 by 512 active pixels formed on a single integrated circuit chip. Some examples of the conventional CMOS image sensors can be seen in U.S. patent application Ser. No. 09/103,959 and U.S. Pat. No. 5,900,623. An image sensor core 19 comprises a two-dimensional pixel array of light detecting elements 10 which include identical circuitry shown in FIG. 1B. When in sensing, an image is focused on the image sensor core 19 such that different portion of the image impinges on each pixel element 10. As shown in FIG. 1B, each light detecting element 10 comprises a photodiode 20, or an equivalent photo sensing device, such as a photogate, bipolar phototransistor, etc., the conducting current of which is proportion to the intensity of the light impinging upon the junction of the photo sensing device.
At the beginning of the exposure cycle, an internal column line 24 is isolated because an access transistor T3 is turned off due to the inactive state of the RD signal. The photodiode 20 is initially reset to a value close to Vref level by means of the reset transistor T1, which is turned on by the active high state of the signal RST output from the row address shift register (not shown). All the operations of the conventional CMOS image core 19 can be illustrated with reference to U.S. patent application Ser. No. 09/103,959 filed on Jun. 24, 1998 by the same applicant, which is incorporated herein by reference.
The exposure commences as the reset transistor T1 is turned off by the inactive state of the signal RST. This allows the photodiode current, due to the light impinging on it, to discharge from the capacitance of the floating node Nd, reducing the charge on node Nd. The exposure time starts at the falling edge of the RST signal and stops at the rising edge of the sequential RST signal. After a sufficient time from the commencement of the exposure time, which may be varied to provide different image sensitivity or exposure control, the access transistors T3 in the row are turned on by an active RD signal for the row. This causes the photodiode voltage at node Nd, translated through the source follower transistor T2 and the access transistor T3, to be coupled to the internal column line 24. The voltage is offset by the source follower transistor T2, and, of course, will vary with the characteristics of the transistor T2. This voltage will be sampled and held in a following correlated-double sampling (CDS) circuit (not shown) at the end of the column line 24. At the end of the exposure interval, the reset transistors T1 in the row are then turned on again, causing the input of the source follower T2, which is coupled to the cathode node P of photodiode 20, to be reset to a value close to the Vref The actual signal sensed by the CDS circuit is the difference of signals at node C, denoted as ΔVc, before and after the reset a signal RST is activated. The subtraction of the signals of the node C at different moments is accomplished by the well known CDS circuitry, which will not be described in detail in this invention. With the above principle, as shown in FIG. 1B, the photodiodes 20 in each row are exposed to generate the current to the column lines in response to the reset signal for the row, i.e., RSTn, n=1 . . . 512 as well as the corresponding read signal RDn, and the reset signal for each row is activated sequentially in time to obtain the voltage differences for all the rows.
In the NTSC (National Television Standards Committee) television system, the television picture, as an example, adopted for a solid state sensor is composed of a plurality of image pixels arranged in 525 horizontal rows. The picture is divided into an odd field and an even field. Odd numbered lines 1, 3, 5, etc. of a television picture are scanned first and displayed in the odd field time. After the odd field has been scanned, even numbered lines 2, 4, 6, etc. of the television picture are scanned and displayed in the even field. The scanning scheme in which the odd field is interlaced with the even field is so-called interlace scanning.
For compatibility reasons, the NTSC scanning scheme has been carried over to the digital camera employing the CMOS image sensor. For a conventional NTSC interlace scanning scheme, the pixel array of 512 by 512 pixels for illustration of simplicity would be first scanned in an order of rows 1, 3, 5, 7, . . . and 511 for the odd field time by sequentially activating the reset signals RSTm, m=1, 3, 5, 7, . . . 511, then rows 2, 4, 6, 8, . . . , and 512 for the even field time by sequentially activating the reset signals RSTm, m=2, 4, 6, 8, . . . 512 under the control of the row address shift register, wherein each field takes roughly {fraction (1/60)} second within the {fraction (1/30)} second frame time. In this conventional method, as shown in FIG. 1B, there are 512 access transistors T3 as well as source follower amplifiers T2, and 512 floating sensing nodes Nd per row in the array. Each floating sensing node Nd is driven by one photodiode.
The analog signals produced by the light detecting elements 10 are apt to be contaminated by the above-mentioned types of noise, causing CMOS active pixel sensors to have lower sensitivity or lower dynamic range as compared to the CCD.
Therefore, improvement of sensitivity or dynamic range becomes a critical technical challenge for CMOS image sensor designers. The present invention intends to increase pixel sensitivity and to improve the overall image quality through a special pixel design arrangement.